1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a nonvolatile semiconductor memory device in which a memory cell array is divided into a plurality of blocks.
2. Description of the Related Art
In nonvolatile semiconductor memory devices, reference-purpose memory cells, which are separate from data memory cells, are used as a reference in determining the level of data that is retrieved from the data memory cells. Such reference memory cells are arranged not as part of a memory cell array but as part of peripheral circuits of the memory cell array. One set of reference memory cells is provided for one memory device. Where a memory cell array is divided into a plurality of blocks, the outputs of the reference cells need to be distributed to sense amplifiers of each one of the blocks.
FIG. 1 is an illustrative drawing for explaining the reading of data from a flash memory device.
In FIG. 1, a memory cell array 11 includes a plurality of memory cell transistors 21, a plurality of word lines WL, and a plurality of bit lines MBL. The memory cell array 11 is a virtual ground memory array in which bit lines are formed by diffusion layers, one bit line of each pair of bit lines that is coupled to the ground potential serving as a source, and the other bit line that is coupled to the power supply potential serving as a drain. In such a virtual ground memory array, bit lines are shared by memory cells that are adjacent to each other in the direction of word-line extension.
A Y gate 12 includes a plurality of transistors 22 and 23. In response to decoding signals CS(0), CS(1), CS(2), BSD(0), BSG(0), and BSP(0) reflecting an address for selecting a bit line, the Y gate 12 selects a bit line MBL of the memory cell array. As a power supply potential for the decoding signals CS(n), a boosted potential VBOOST_CSG is used that is generated by boosting a power supply potential VCC inside the device. The Y gate 12 is shown in a simplified form for the sake of illustration in FIG. 1, but actually has a plurality of transistors 22 and 23 arranged in such a manner as to select a bit line MBL corresponding to a single memory cell from a plurality of bit lines MBL.
A sensing circuit 13 includes transistors 24 through 26, a sense amplifier 27, a current-to-voltage conversion circuit 28, and a precharge circuit 29.
The bit line MBL that serves as a drain of a memory cell being accessed for reading data from the memory cell array 11 is coupled to the current-to-voltage conversion circuit 28 as DATAB through a transistor 23 that is coupled to BSD(0) in the Y gate 12. The boosted potential VBOOST_CSG is used as a power supply potential for BSD(0). The output of the current-to-voltage conversion circuit 28 is supplied to the sense amplifier 27.
The bit line MBL that serves as a source of the memory cell being accessed for reading data from the memory cell array 11 is coupled to the drain of the transistor 25 as ARVSS through a transistor 23 that is coupled to BSG(0) in the Y gate 12. The power supply potential VCC is used as a power supply potential for BSG(0). During a routine read operation, SPVB that is applied to the gate node of the transistor 25 is set to HIGH, thereby coupling ARVSS to the ground potential.
A bit line adjacent to the bit line that is serving as the drain of the read-accessed memory cell is coupled to the precharge circuit 29 as DATABP through a transistor 23 that is coupled to BSP(0) in the Y gate 12. The boosted potential VBOOST_CSG is used as a power supply potential for BSP(0). The precharge circuit 29 charges the bit line that is adjacent to the bit line serving as the drain at the time of memory cell reading. The precharge circuit 29 has the same circuit structure as the current-to-voltage conversion circuit 28, and supplies a potential to the adjacent bit line that is the same as the potential that is set to the drain bit line. With this provision, no current runs across these bit lines, providing for only the current of the accessed memory cell to be detected by the current-to-voltage conversion circuit 28.
A similar circuit structure is provided for a reference-cell portion so as to attain the same operation as that performed on the memory-cell portion.
A reference-cell circuit 14 includes a plurality of cell transistors 31 having the same structure as the memory-cell transistors 21, and further includes a word line SBSR for reading a reference cell 31 (shown as encircled) that is one of the cell transistors.
A reference Y gate 15 includes a plurality of transistors 32 and 33. The transistors 32 are driven by the boosted potential VBOOST_CSG. Transistors 33 that correspond to the drain bit line and the adjacent bit line are driven by the boosted potential VBOST_CSG, and a transistor 33 that corresponds to the source bit line is driven by the power supply potential VCC.
A reference load circuit 16 includes a transistor 34, a current-to-voltage conversion circuit 35, and a precharge circuit 36. The reference load circuit 16 put the load on a signal read from the reference cell where the load is the same as that imposed on a signal that is read from the read-accessed memory cell of the memory cell array 11. In this manner, the reference load circuit 16 makes sure that the memory data signal and the reference signal are compared with each other under the same conditions.
The bit line serving as the drain of the reference cell 31 is coupled to the current-to-voltage conversion circuit 35 as DATABX through the reference Y gate 15. An output SAREF of the current-to-voltage conversion circuit 35 is supplied to the sense amplifier 27 of the sensing circuit 13.
A bit line that serves as the source of the reference cell 31 is coupled to the drain of the transistor 34 as GARVSS through the reference Y gate 15. During a routine read operation, SPVB_REFEX that is applied to the gate node of the transistor 34 is set to HIGH, thereby coupling GARVSS to the ground potential VSS.
A bit line adjacent to the drain bit line of the reference cell 31 is coupled to the precharge circuit 36 as DATAB_PRE through the reference Y gate 15. The precharge circuit 36 charges the bit line that is adjacent to the bit line serving as the drain at the time of memory cell reading. The precharge circuit 36 has the same circuit structure as the current-to-voltage conversion circuit 35, and supplies a potential to the adjacent bit line that is the same as the potential being set to the drain bit line. With this provision, no current runs across these bit lines, providing for only the current of the reference cell 31 to be detected by the current-to-voltage conversion circuit 35.
When the memory cell transistor 21 that is encircled in FIG. 1 is read, WL(2) is selectively activated, and the Y gate 12 selects relevant bit lines. The word line SBSR of the reference-cell circuit 14 is also activated. SPVB, SPVP_REFEX, PGMDB, and MUXDATAPB are all set to HIGH, and GARVSS and ARVSS are set to the ground potential VSS, with DATABP and DATAB_PRE being short-circuited. The sense amplifier 27 compares a current of the reference cell 31 with a current Ic of the memory cell 21. If Ic is larger, data is ascertained to be “1”. Otherwise, data is ascertained as “0”.
Even if the potential of ARVSS rises due to an increase of the current of ARVSS, GARVSS will have the same potential rise since the short-circuiting of ARVSS and GARVSS. This ensures that the read conditions are always the same between the reference cell and the read-accessed memory cell. By the same token, DATABP and DATAB_PRE are short-circuited, so that the read conditions are always the same between the reference cell and the read-accessed memory cell.
There is a related-art document that discloses a reference cell array and a plurality of cell arrays (Japanese Patent Application Publication No. 2001-143487).
When the memory cell array 11 is divided into four blocks, for example, the sensing circuit 13 needs to be provided for each of the four blocks. If a single set of the reference-cell circuit 14, the reference Y gate 15, and the reference load circuit 16 is provided for shared use by the four blocks, the following problems will be encountered.
Device characteristics may differ from device to device due to differences in device positions and layouts. The reference circuit may have matching characteristics with the first block, which provides proper data sensing. This reference circuit may not have matching characteristics with other blocks, resulting in data sensing being unable to be properly performed. If the boosted potential VBOOST_CSG differs between the reference Y gate 15 and the Y gate 12 that are positined apart from each other, the output of the Y gate 12 cannot be properly compared with the output of the reference Y gate 15.
In this manner, circuit characteristics and drive potentials vary from block to block. This gives rise to a problem that no sensible comparison can be made for data sensing between the reference cell and a memory cell of each block.
Accordingly, there is a need for a nonvolatile semiconductor memory device that ensures proper comparison between a reference circuit and each memory cell block when a memory cell array is divided into a plurality of blocks.